1. Field of the Invention
Embodiments of the invention relate to plasma enhanced etch processes. More particularly, embodiments of the invention relate to plasma etch processes useful in etching metals, such as tungsten and tungsten nitride, formed on thin dielectric materials in gate applications.
2. Description of the Related Art
Metal etching in gate applications with the metal film formed directly on the gate dielectric material is one of the most challenging processes in gate applications. Most metal films, such as tungsten and tungsten nitride, can be etched easily with fluorine containing species. However, fluorine containing species also etch the underlying gate dielectric at a substantial etch rate. Thus, selectivity between the metal film and the gate dielectric layer is difficult to maintain. Non-fluorine containing chemistry such as Cl2 and O2 chemistry can maintain adequate selectivity, but a large amount of oxidized tungsten byproduct deposition results and makes control of the gate profile very difficult. In addition, the residues or byproducts formed on a substrate as a result of Cl2 and O2 chemistry are hard to remove after the etching process is completed.
In gate applications, polysilicon has typically been used between the tungsten electrode and the gate dielectric. The polysilicon in these applications serves as a good etch stop for the tungsten etch process because the chemistry used to etch tungsten has good selectivity between tungsten and the polysilicon. Following the removal of tungsten using a fluorine based chemistry, the polysilicon can be removed with HBr and O2 chemistry which has good selectivity between the polysilicon and the underlying gate dielectric. The HBr and O2 chemistry is selective for the polysilicon and can be stopped on the underlying gate dielectric without damage to the gate dielectric.
In recent gate applications, a metal layer and a metal barrier layer, such as a metal nitride layer (e.g., tungsten and tungsten nitride) are formed on the gate dielectric. The polysilicon layer is preferably eliminated in these newer devices to provide increased speed of the device. With the elimination of the polysilicon layer as an etch stop, a process must be utilized which provides good etch rate uniformity and profile uniformity across the substrate surface while maintaining mask selectivity, i.e., etching selectivity between a hard mask on top of the gate electrode and the gate electrode. The process must also provide etching selectivity between the tungsten and the gate dielectric. However, process chemistry and conditions may often have opposite effect on profile control and gate dielectric selectivity. It can be difficult to maintain a balance between a good gate profile and high gate dielectric selectivity simultaneously. Etch processes which can be used to remove tungsten with good selectivity to gate dielectrics may result in the formation of large amounts of non-volatile byproducts, mainly WO3, which deposit on the gate electrode and the hard mask on top of the gate electrode. The deposition of non-volatile byproducts can cause a significantly reduced etch rate and a tapered profile. The non-volatile byproducts are typically difficult to remove after the etching process.
Therefore, there is a need for a process for etching metals in gate applications in which the metal is formed on the gate dielectric, such as a gate oxide, without an etch stop being formed therebetween.